1. Field of the Invention
The present invention relates generally to the field of digital communications. Specifically, the present invention relates to synchronizing digital receivers to symbol timing. More specifically, the present invention relates to recovering symbol timing in a received signal by controlling a sampling device such that in-phase (I) and quadrature (Q) components of the received signal are sampled at a symbol rate.
2. Description of the Related Art
The efficient functioning of modern data communications systems using bidirectional digital data communication requires clock and data recovery circuitry. The ability to regenerate binary data is an inherent advantage of transmitting information digitally as opposed to transmitting such information in analog form. However, in order for the intelligence signal to be correctly reconstructed at the receiving end, the transmitted binary data must be regenerated with the fewest possible number of bit errors, requiring received data to be sampled at an optimum sample rate and at an optimum instance of time. Due to limited bandwidth, it is generally impractical to transmit the required sampling clock signal separate from the transmitted data signal. As a result, modern digital communication systems derive timing information from the incoming transmitted data signal itself. Extraction of the implicit timing signal is generally termed timing recovery (or clock recovery).
Modern digital communication receivers perform timing recovery using symbol synchronization. Symbol synchronization in a digital communication receiver refers to identifying the-instants in time at which samples of an input communication signal are best obtained to recover data conveyed by the input communication signal. Only one sample is needed per symbol interval to accurately recover communicated data. A symbol interval, also called a unit interval or simply a symbol, is a discrete duration within which a received signal conveys a unit of data. The unit of data may include one or more bits. The process of symbol synchronization determines the best instant within each symbol interval at which to obtain a sample that will be relied upon in the recovery of the unit of data.
A block diagram of a conventional symbol timing recovery system for providing symbol synchronization is shown in FIG. 1. Phase detector 102 provides an error signal to an input of loop filter 104, the output of which provides an input to timing oscillator 106 which produces the recovered clock as an output. This information is essentially a sampling clock for controlling the symbol sampling operation of sampling device 108.
In conventional symbol timing recovery systems, timing oscillator 106 can be either a voltage controlled oscillator or a numerically controlled oscillator (NCO). The recovered clock is applied to a control input of sampling device 108, which captures symbol data at “windows” of the received signal pattern. Sampling device 108 may comprise an analog-to-digital converter (ADC).
The use of these conventional timing oscillators in symbol timing recovery systems requires the use of expensive high speed components and/or the use of excessively complex circuits. For example, if an NCO is used as the timing oscillator, it is a requirement that the NCO be operated at a high frequency in order to provide enough resolution to provide for optimum sampling. Thus, typically the NCO must be clocked at a frequency that is, for example, 16 to 32 times the symbol rate.
In order to provide a high speed clock for the NCO, a high frequency crystal oscillator may be provided. However, such a high frequency crystal oscillator is expensive. Thus, although the NCO provides excellent resolution to provide for optimum sampling, it adds greatly to the cost of the symbol timing recovery system.
As an alternative to providing the high frequency crystal oscillator to clock the NCO, a phase locked loop (PLL) may be provided in combination with a less expensive crystal oscillator having a frequency closer to the symbol rate. The PLL multiplies the crystal oscillator frequency to be 16 to 32 times the symbol rate at its output. The output of the PLL is then provided to the NCO. However, the PLL/crystal oscillator combination requires additional circuitry and thus adds to the complexity of the symbol timing recovery system.
Another conventional timing oscillator used in symbol timing recovery systems is a voltage controlled oscillator (VCO). The digital data may be converted by a digital to analog converter (DAC) to an analog signal. The analog signal is then input to the VCO. The output of the VCO then provides the appropriate frequency and phase to the sampling device 108. Although, using of a VCO for the timing oscillator avoids any requirement of for a high speed crystal oscillator, it still requires additional circuitry and thus adds to the complexity of the symbol timing recovery system.
Thus, there remains a need for an inexpensive and low-complexity symbol timing recovery system.